The semiconductor industry has experienced rapid growth and demands for highly integrated semiconductor devices are increasing. However, these demands have increased the complexity of processing and manufacturing semiconductor devices for integrated circuits (ICs) and, for these demands to be met, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density has generally increased while geometric size (i.e., the smallest component (or line) that can be created through a fabrication process) has decreased.
For example, as the size of features is scaled down, it may be difficult to form these features having the desired size using conventional photolithography processes because the wavelength of the light sourced for these photolithography processes is reaching its technical limitations.
To address this drawback, a double patterning technology has been developed to form the semiconductor features having small geometric sizes. In the double patterning method, mandrels are formed over a layer to be etched by photolithography and etching processes. Afterwards, spacers are formed on the sidewalls of the mandrels. The mandrels are then removed to leave the spacers that are used as an etch mask for definition of the underlying layer.
Although existing doubling patterning methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.